x86/mce: assorted fixes

- correct various range checks (avoids bogus warnings on domains
  modifying virtualized MSRs)
- correct consistency check (so that APs get checked instead of the
  BP [against uninitialized data])
- reduce verbosity (capabilities printed only once, but then all of
  the relevant values)

Signed-off-by: Jan Beulich <jbeulich@novell.com>

diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h
index a66fe2c1fc65ae0daa6d22ac9cd96dbe92184d77..d27cd6b409d4970c32d1573ccb1770d6f52cdd35 100644 (file)
--- a/xen/arch/x86/cpu/mcheck/mce.h
+++ b/xen/arch/x86/cpu/mcheck/mce.h
@@ -174,15 +174,14 @@ extern unsigned int nr_mce_banks;
 static inline int mce_vendor_bank_msr(uint32_t msr)
 {
     if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
-        (msr > MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks)) )
+         msr >= MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks) )
           return 1;
     return 0;
 }
 
 static inline int mce_bank_msr(uint32_t msr)
 {
-    if ( (msr > MSR_IA32_MC0_CTL2 &&
-         msr < (MSR_IA32_MCx_CTL(nr_mce_banks - 1))) ||
+    if ( (msr >= MSR_IA32_MC0_CTL && msr < MSR_IA32_MCx_CTL(nr_mce_banks)) ||
         mce_vendor_bank_msr(msr) )
         return 1;
     return 0;

diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c
index 838acc95e22da5ca79060447d18e70937ce3a10c..14af3f888010e0636372e83f29d3c53df7c4d67e 100644 (file)
--- a/xen/arch/x86/cpu/mcheck/mce_intel.c
+++ b/xen/arch/x86/cpu/mcheck/mce_intel.c
@@ -1146,26 +1146,26 @@ static void intel_init_mca(struct cpuinfo_x86 *c)
 
     first = mce_firstbank(c);
 
-    dprintk(XENLOG_INFO, "MCA Capaility: CPU %x SER %x"
-       "CMCI %x firstbank %x extended MCE MSR %x\n",
-       smp_processor_id(), ser, cmci, first, ext_num);
-
-    if (smp_processor_id())
+    if (smp_processor_id() == 0)
     {
+        dprintk(XENLOG_INFO, "MCA Capability: BCAST %x SER %x"
+                " CMCI %x firstbank %x extended MCE MSR %x\n",
+                broadcast, ser, cmci, first, ext_num);
+
         mce_broadcast = broadcast;
         cmci_support = cmci;
         ser_support = ser;
         nr_intel_ext_msrs = ext_num;
         firstbank = first;
     }
-    else
+    else if (cmci != cmci_support || ser != ser_support ||
+             broadcast != mce_broadcast ||
+             first != firstbank || ext_num != nr_intel_ext_msrs)
     {
-        if (cmci != cmci_support || ser != ser_support ||
-            broadcast != mce_broadcast ||
-            first != firstbank)
-            dprintk(XENLOG_WARNING,
-              "CPU %x has different MCA capability with BSP\n"
-              "may cause undetermined result!!!\n", smp_processor_id());
+        dprintk(XENLOG_WARNING,
+                "CPU %u has different MCA capability (%x,%x,%x,%x,%x)"
+                " than BSP, may cause undetermined result!!!\n",
+                smp_processor_id(), broadcast, ser, cmci, first, ext_num);
     }
 }
 
@@ -1265,8 +1265,7 @@ int intel_mce_wrmsr(uint32_t msr, uint64_t val)
 {
     int ret = 0;
 
-    if (msr > MSR_IA32_MC0_CTL2 &&
-        msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1))
+    if (msr >= MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks))
     {
         mce_printk(MCE_QUIET, "We have disabled CMCI capability, "
                  "Guest should not write this MSR!\n");
@@ -1280,8 +1279,7 @@ int intel_mce_rdmsr(uint32_t msr, uint64_t *val)
 {
     int ret = 0;
 
-    if (msr > MSR_IA32_MC0_CTL2 &&
-        msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks - 1))
+    if (msr >= MSR_IA32_MC0_CTL2 && msr < (MSR_IA32_MC0_CTL2 + nr_mce_banks))
     {
         mce_printk(MCE_QUIET, "We have disabled CMCI capability, "
                  "Guest should not read this MSR!\n");